Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often desire to design architectures that are not only compact, but offer performance advantages, as well as simplified designs.
A relatively common semiconductor device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of a memory cell is a dynamic random access memory (DRAM) cell. In the simplest design configuration, a DRAM cell includes one access device, such as a transistor, and one storage device, such as a capacitor. Modern applications for memory devices can utilize vast numbers of DRAM cells, arranged in an array of rows and columns. The DRAM cells are electrically accessible through digit lines and word lines arranged along the rows and columns of the array.
FIG. 1 illustrates a transistor 10 of a conventional DRAM cell. The transistor 10 includes an active area 12 extending between neighboring word lines 14 and shallow trench isolation (STI) regions 16 extending between neighboring active areas 12 to isolate the active areas 12 from one another. An oxide region 18 is provided about the word lines 14 between the word lines 14 and the active area 12 and the STI region 16, respectively. Each word line 14 is provided with a word line cap 20. A digit line contact 22 (e.g., digit line plug) is formed on the active area 12 in a digit line contact opening 30 (FIG. 11) defined by surfaces 25 of a conductive region 26, an oxide region 27, and laterally-neighboring word line caps 20. A digit line 24 is electrically connected to the digit line contact 22. The digit line 24 includes a polysilicon region 21 and another conductive region 23 formed adjacent longitudinally adjacent, on, over) to the oxide region 27 and another polysilicon region (e.g., the conductive region 26) that each neighbor the digit line contact 22. A digit line cap 28 is formed adjacent to the digit line 24.
As illustrated in FIG. 1 and in FIG. 11, which is discussed in further detail below, the word line caps 20 are etched during formation of the of the transistor 10 such that at least a portion of the word line caps 20 are removed. Accordingly, the respective word line caps 20 may have a recess formed therein and defined by a sloped surface 13 and a substantially horizontal surface 15. The word line caps 20 are etched such that the sloped surface 13 extends to and intersects with the substantially horizontal surface 15 at a transition surface 17 (e.g., corner) that projects into the word line cap 20 and away from a longitudinal axis 31. Accordingly, the opening 30 in which the digit line contact 22 is formed is substantially U-shaped.
A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices. While a footprint of the memory devices of memory cells, including transistors, continues to be scaled down to increase the memory density, decreasing the size of one or more components of memory cells may negatively affect performance and places ever increasing demands on the methods used to form the memory device features. For example, one of the limiting factors in the continued shrinking of memory devices is the resistance of the contacts associated therewith. For example, in a DRAM device exhibiting a dual bit memory cell structure, the digit line contact 22 is provided between the digit line 24 and an access device (e.g., a transistor) formed in or above a substrate, and storage node contacts are formed between the access device and a storage node (e.g., a capacitor) where electrical charge may be stored. As the dimensions of memory device (e.g., DRAM device) features decrease, the distance between neighboring digit line contacts of the memory arrays decreases, increasing coupling capacitances between the adjacent (e.g., laterally-neighboring) digit line contacts. With greater amounts of coupling capacitances between the adjacent digit line contacts, current and voltage pulses used to select memory cells can, undesirably, be distributed to neighboring memory cells in a memory array and thus reduce the reliability of the neighboring memory cells and the memory array as a whole.